1. Field of the Invention
The invention relates to integrated circuits, and particularly to memory system designs of a cache architecture.
2. Description of Related Art
In a mobile society at the start of a new millennium, a challenge in designing a compact or handheld device is to extend the battery power duration after a charge-up. A cache is an integral part of a computing system but draws a significant amount of system power. A design trend in the past has a dominant focus on finding new ways to increase the speed of a computing system. However, prolonging a battery power has become a primary focus in the design of wireless and mobile devices.
A cache refers to a storage architecture in integrated circuits and software where the most commonly used data is tagged and stored for quick retrieval. A principle usage of a cache is to speed-up processing of information of an application program. A cache tags a piece of data or information using a tagging algorithm. The tag itself and the related data are stored. When a processor seeks to retrieve a piece of data, the same tagging algorithm is applied to generate a tag in which the tag is used to identify whether the data exists in the cache.
FIG. 1 is a prior art diagram illustrating a conventional two-way associativity cache architecture 10. Cache architecture 10 includes two one-way of associativities 11 and 12. An address decoder 13 decodes an index address 25 for use in a tag array 14, and a separate address decoder 16 is used for a data array 17 in associativity 11. Similarly, an address decoder 19 is used for a tag array 20, and a separate address decoder 22 is used for a data array 23 in associativity 12. The same index line 25 is fed feed to all four address decoders 13, 16, 19, and 22.
When index line-25 is received by cache architecture 10, all four address decoders 13, 16, 19, and 22 are powered-up. A tag look-up and a data look-up are performed simultaneously in tag array 14, data array 17, tag array 20, and data array 23. A comparator 15 compares the tag from tag array 14 with a tag compare data 26 in associativity 11, while a comparator 21 compares the tag from tag array 20 with a tag compare data 26 in associativity 12. One of the two data enables 18 and 24 is enabled to generate the output on a data bus 27. A shortcoming of this conventional cache architecture 10 is that a large amount of power is consumed by simultaneous activation of tag array 14, tag array 20, data array 17, and data array 23. When additional associativities are stacked over existing associativities, cache architecture draws an even greater amount of power as well as causing potential timing problems.
Accordingly, it is desirable to have a cache architecture that is modular and scalable that consumes low-power.